Power Modules Having an Integrated Clamp Circuit and Process Thereof

ABSTRACT

A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.

CROSS REFERENCE TO PRIOR APPLICATIONS

This application is a continuation in part of U.S. patent application Ser. No. 15/382,172, filed Dec. 16, 2015, which is incorporated herein by reference in its entirety. This application also claims the benefit from U.S. Provisional Patent Application No. 62/462,552 filed on Feb. 23, 2017, which is hereby incorporated by reference for all purposes as if fully set forth herein.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with Government support by the Army Research Laboratory: Contract No. W911NF-16-2-0132. The United States government has certain rights in the invention.

BACKGROUND OF THE DISCLOSURE 1. Field of the Disclosure

This disclosure is directed to power modules having an integrated clamp circuit. Moreover, the disclosure is directed to a process of configuring power modules that include an integrated clamp circuit.

2. Related Art

As will be appreciated by those skilled in the art, power modules are known in various forms. Power modules provide a physical containment for power components, usually power semiconductor devices. These power semiconductors are typically soldered or sintered on a power electronic substrate. The power module typically carries the power semiconductors, provides electrical and thermal contact, and includes electrical insulation.

One of the common problems faced when operating a power module is inadvertent operation due to parasitic current and/or voltage signals. For example, higher changes in voltage over time during a switching operation can induce a parasitic turn on of a switch in the power module. A number of approaches have been utilized to address this inadvertent operation in associated driver circuitry. However, these approaches have been less than satisfactory.

Accordingly, what is needed is a power module configured to limit inadvertent operation due to parasitic signals in order to enable proper control of the power module.

SUMMARY OF THE DISCLOSURE

In one aspect, a power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate, a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, a clamping circuit electrically connected to the at least one power device, and the clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.

In another aspect, a power module apparatus includes a power substrate positioned relative to a base plate, at least one power device electrically connected to at least two power contacts, a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a clamping circuit electrically connected to the at least one power device, the clamping circuit configured to clamp an input to a gate of the at least one power device, where the clamping circuit is configured to clamp a voltage at the gate of the at least one power device to less than 8 V peak to peak.

In another aspect, a power module apparatus includes a power substrate positioned relative to a base plate, at least one power device electrically connected to at least two power contacts, a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, and a clamping circuit electrically connected to the at least one power device, the clamping circuit configured to clamp an input to a gate of the at least one power device, where the clamping circuit is configured to reduce a voltage charge up at the gate of the at least one power device by at least 10%.

Additional features, advantages, and aspects of the disclosure may be set forth or apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary of the disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the disclosure as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and together with the detailed description serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and the various ways in which it may be practiced. In the drawings:

FIG. 1 illustrates a schematic view of a power module according to an aspect of the disclosure.

FIG. 2A illustrates a schematic view of an implementation of the power module of FIG. 1.

FIG. 2B illustrates a schematic view of another implementation of the power module of FIG. 1.

FIG. 3 illustrates an exemplary sense and control circuit according to one aspect of the disclosure.

FIG. 4 illustrates a structural implementation of the power module of FIG. 1.

FIG. 5 illustrates an exploded view of the power module of FIG. 4.

FIG. 6 illustrates a relative size to thickness comparison of the power module of FIG. 4.

FIG. 7 illustrates a current flow for multiple paralleled devices of the power module of FIG. 4.

FIG. 8 illustrates the power contact configuration of the power module of FIG. 4.

FIG. 9 illustrates the low profile power contact of the power module of FIG. 4.

FIG. 10 illustrates the power module base plate of the power module of FIG. 4.

FIG. 11 illustrates the gate-source PCB of the power module of FIG. 4.

FIG. 12 illustrates the gate-source PCB having a half bridge arrangement of the power module of FIG. 4.

FIG. 13 illustrates the gate-source PCB having a common source/emitter arrangement of the power module of FIG. 4.

FIG. 14 illustrates the gate-source PCB having a common drain/collector arrangement of the power module of FIG. 4.

FIG. 15 illustrates a single layer modular gate-source PCB example layout of the power module of FIG. 4.

FIG. 16 illustrates the power substrate half bridge arrangement of the power module of FIG. 4.

FIG. 17 illustrates the power substrate common source/emitter arrangement of the power module of FIG. 4.

FIG. 18 illustrates the power substrate common drain/collector arrangement of the power module of FIG. 4.

FIG. 19 illustrates the housing topside features of the power module of FIG. 4.

FIG. 20 illustrates the housing backside features of the power module of FIG. 4.

FIG. 21 illustrates the housing separated from the power module assembly of the power module of FIG. 4.

FIG. 22 illustrates the power contact guides of the power module of FIG. 4.

FIG. 23 illustrate the half bridge, single channel common source/emitter or drain/collector module of the power module of FIG. 4.

FIG. 24 illustrates the full bridge, dual channel common source/emitter or drain/collector module of the power module according to another aspect of the disclosure.

FIG. 25 illustrates the extended single housing side-by-side module configuration of the power module according to another aspect of the disclosure.

FIG. 26 illustrates a clamped inductive load (CIL) test fixture schematic to provide test performance data for power modules.

FIG. 27 illustrates graphs of test data for a power module with no gate clamping.

FIG. 28 illustrates graphs of test data for a power module with a clamping circuit located on a gate driver.

FIG. 29 illustrates graphs of test data for a power module with a clamping circuit located with the power module in accordance with the disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

The aspects of the disclosure and the various features and advantageous details thereof are explained more fully with reference to the non-limiting aspects and examples that are described and/or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and features of one aspect may be employed with other aspects as the skilled artisan would recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as to not unnecessarily obscure the aspects of the disclosure. The examples used herein are intended merely to facilitate an understanding of ways in which the disclosure may be practiced and to further enable those of skill in the art to practice the aspects of the disclosure. Accordingly, the examples and aspects herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Moreover, it is noted that like reference numerals represent similar parts throughout the several views of the drawings.

FIG. 1 illustrates a schematic view of a power module according to an aspect of the disclosure. As shown in FIG. 1, one exemplary aspect of the disclosure is generally shown as a power module 100. The power module 100 may be configurable in a number of useful power electronic topologies such as half bridge, full bridge, common source/emitter, common drain/collector, and the like. The power module 100 can be configured in two, four, six, or more separate channels. Moreover, the power module 100 can be configured with any number of separate channels.

The power module 100 may include a number of elements including a base plate 200, a power substrate 300, power contacts 400 (shown in FIG. 5), power devices 500, a gate-source printed circuit board (PCB) 600, gate drive connectors 700, and a housing 800. The power module 100 further includes a clamp circuit 104. The clamp circuit 104 is arranged in or on the power module 100. The arrangement of the elements illustrated in FIG. 1 is merely for illustrating the various locations of the clamp circuit 104 and not necessarily indicative of the arrangement and positioning of the elements. Moreover, it is contemplated that the power module 100 may include fewer, more, or different elements than those described herein.

A gate driver 102 may be arranged separate from the power module 100 and may be connected to the power devices 500 of the power module 100 along a signal line 106. The gate driver 102 may provide one or more gate drive signals to the power devices 500 along the signal line 106. The gate driver 102 can be any type of driver. The gate driver 102 may be a bipolar driver, a high performance driver, a higher frequency switching driver, a driver having structure for handling current of 10 to 15 amps (A), a driver having structure for handling any amount of current, and the like. The gate driver 102 may be any type of driver configured for driving the disclosed power devices 500.

The clamp circuit 104 may be arranged in or on the power module 100. In one aspect, the clamp circuit 104 may be arranged on or with the gate-source PCB 600 as indicated by arrow 108. In one aspect, the clamp circuit 104 may be arranged on or with the base plate 200 as indicated by arrow 110. In one aspect, the clamp circuit 104 may be arranged on or with the power substrate 300 as indicated by arrow 112. In one aspect, the clamp circuit 104 may be arranged on or with the gate drive connectors 700 as indicated by arrow 114. In one aspect, the clamp circuit 104 may be arranged on or with the housing 800 as indicated by arrow 116. In one aspect, the clamp circuit 104 may be arranged on the power module 100. In one aspect, the clamp circuit 104 may be arranged inside the power module 100. In one aspect, the clamp circuit 104 may be arranged on the power contacts 400. In one aspect, the clamp circuit 104 may be arranged on the power devices 500. In one aspect, the clamp circuit 104 may be arranged in the power devices 500. Each of these locations of the clamp circuit 104 being defined as being in close physical proximity to the power module 100 or integrated into the power module 100.

In one aspect, the clamp circuit 104 may be a Miller Clamp. In another aspect, the clamp circuit 104 may be an active Miller Clamp. The clamp circuit 104 may enable a gate of the power devices 500 to be held off in a presence of a rapid change in voltage on a drain/collector of the power devices 500. The rapid change in voltage on a drain/collector being one cause of parasitic turn on. The parasitic turn on may also be characterized by excessive turn off induced voltage spikes, unwanted charging of a gate, parasitic inductance between a gate and the power module, Miller induced turn on, parasitic Miller capacitance, Miller induced charge-up, and/or the like that degrades proper controlling of the power module. The clamp circuit 104 may be configured to hold the gate of one of the power devices 500 low so that any disturbance seen on the gate may be minimized and/or eliminated. To better control the gate of the power devices 500, the clamp circuit 104 may be placed in close physical proximity to the gate of the power device 500 it is intended to control as shown in FIG. 1. Placing the clamp circuit 104 in close physical proximity to the power module 100 improves performance of the power devices 500. Moreover, placing the clamp circuit 104 in close physical proximity to the power module 100 reduces customer complexity with respect to operation and control of the power module 100. In this regard, the driver complexity and operation may be greatly simplified by utilization of the clamp circuit 104 of the disclosure implemented in the power module 100. In one aspect, a driver operating a power module 100 according to the disclosure does not have to account for potential parasitic turn on issues thus reducing the complexity of the driver. Moreover, physical coupling, arrangement, and location in close physical proximity to the power module 100 enables better gate control of the power devices 500 and allows the clamp circuit 104 to hold the gate off much better than prior art implementations placed with a gate driver outside a power module.

In operation, the clamp circuit 104 limits and reduces the effect of undesired voltage and/or currents input to a gate of the power devices 500. In other words, the clamp circuit 104 clamps the input to the gate of the power devices 500 to inhibit undesired operation of the power devices 500 such as parasitic turn on.

In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 10%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 20%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 40%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 60%.

In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to than less than 10 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to than less than 8 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to than less than 7 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to than less than 6 V.

In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to a range of 4-10 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to a range of 2-10 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to a range of 4-6 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 to a range of 2-6 V. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by at least 10%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by at least 20%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by at least 40%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by at least 60%. In one aspect, the clamp circuit 104 may reduce a peak to peak voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by at least 80%.

In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 10%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 20%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 40%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 60%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 64%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 70%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented without a clamp circuit by at least 80%.

In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 10%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 20%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 40%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 60%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 62%. In one aspect, the clamp circuit 104 may reduce a maximum voltage applied to the gate of the power devices 500 in comparison to a power module implemented with a clamp circuit implemented in a gate driver by 80%.

In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 10 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 8 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 6 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 5 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 4 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 3 V of the desired voltage. In one aspect, the clamp circuit 104 may ensure a voltage applied to the gates of the power devices 500 is within 2 V of the desired voltage.

The clamp circuit 104 may be implemented with a plurality of clamp circuits. For example, a clamp circuit 104 for each channel of the power module 100. In one aspect there are two clamp circuits 104. In one aspect there are four clamp circuits 104. In one aspect there are six clamp circuits 104. In one aspect, each of the power devices 500 may include a clamp circuit 104. Moreover, the power module 100 can be configured with any number of channels and with any number of clamp circuits 104 per channel.

Implementations of the disclosed clamp circuit 104 reduce the issues with respect to a shoot through event within the power module 100, which results in inadvertent operation of the power devices 500, such as parasitic turn on. Moreover, the clamp circuit 104 provides better controllability of the power module 100 and the power devices 500. In this regard, placing the clamp circuit 104 in close physical proximity to the power devices 500 reduces parasitics. For example, parasitic resistance, parasitic induction, high impedance, and the like, which all are increased when switching at a high-frequency. Moreover, parasitic resistance, parasitic induction, high impedance, and the like may all be increased when the clamp circuit is located outside a power module. The parasitics are at least one cause of parasitic turn on.

Additionally, the resulting gate driver structure of the gate driver 102 may have reduced complexity. Furthermore, the gate driver 102 implemented with the power module 100 of the disclosure avoids the need for a bipolar driver. Additionally, the location of the clamp circuit 104 helps to avoid undesired switching (e.g., parasitic turn on affect) of the power devices 500 which increases robustness, reliability, reduces failures, and the like of the power module 100. In this regard, parasitic turn on of the power module 100 has a detrimental impact that reduces device life.

The operation of the clamp circuit 104 may be controlled with a sense and control circuit or the like. In this regard, the clamp circuit 104 may be discretely operated by input of an input signal signaling the clamp circuit 104 to clamp the voltage and/or current input to the gate of the power devices 500. Similarly, the clamp circuit 104 may be discretely operated by input of an input signal signaling the clamp circuit 104 to not clamp the voltage and/or current input to the gate of the power devices 500. In this regard, the clamp circuit 104 input may be an input signal to control the operation of the clamp circuit 104. The control signal may be generated by logic that is self-controlled. The logic may be a hardwired circuit comprising logic gates. For example a single converter. In one aspect, the control signal logic may operate as a function of a current switching state of one of the power devices 500. In one aspect, the control signal logic may operate as a function of a current desired switching state of one of the power devices 500. In one aspect, the control logic may be configured to actuate the clamp circuit 104 at least partially during the time when the power device 500 is switched off. In one aspect, the control logic may be configured to deactivate the clamp circuit 104 at least partially during the time when the power device 500 is switched on. In another aspect, the control logic may be configured to actuate the clamp circuit 104 during the time when the power device 500 is switched off. In another aspect, the control logic may be configured to deactivate the clamp circuit 104 during the time when the power device 500 is switched on. In one aspect, the control logic may be configured to actuate the clamp circuit 104 at least partially during the time when the gate driver 102 switches off the power device 500. In one aspect, the control logic may be configured to deactivate the clamp circuit 104 at least partially during the time when the gate driver 102 switches on the power device 500. In one aspect, the control logic may be configured to actuate the clamp circuit 104 during the time when the gate driver 102 switches off the power device 500. In one aspect, the control logic may be configured to deactivate the clamp circuit 104 during the time when the gate driver 102 switches on the power device 500.

In one aspect, the power devices 500 may include a switching device such as a power Field Effect Transistor (FET). However, the power device 500 may be implemented with any type of transistor or switch. For example, the power devices 500 may include any device having a Metal-Oxide Semiconductor (MOS) front end including a MOSFET, a silicon carbide MOS, a trench MOS, an insulated-gate bipolar transistor (IGBT), any MOS structure, and/or the like and combinations thereof. In one aspect, the power devices 500 may include one or more diodes. In one aspect, the power devices 500 may include one or more diodes and may include one or more switching devices.

The base plate 200 may provide mechanical support, heat spreading, and a structure to effectively attach the power module 100 to a heat sink or a cold plate. The material properties of the base plate 200 become increasingly important as the temperature of operation elevates. The base plate 200 material may be selected with consideration of the coefficient of thermal expansion (CTE) where materials in the assembly could otherwise expand at different rates due to heat and create large stresses at their interfaces.

The base plate 200 may utilize a Metal Matrix Composite (MMC) material, which may be a composite of a high conductivity metal, copper, aluminum, etc., and either a low CTE metal such as molybdenum, beryllium, tungsten, or the like and/or a nonmetal such as silicon carbide, beryllium oxide, graphite, or the like. These composite materials may combine features of each contributing element, allowing for a high thermal conductivity with a CTE which may be substantially matched with the power substrate 300 to which it is attached.

The power substrate 300 may be a metal-ceramic-metal layered structure. Of course, other materials may be utilized for the power substrate 300. The power substrate 300 may be configured and designed to handle very high currents and voltages. Metals of the structure may be copper, aluminum, or the like at varying thicknesses, while the ceramic materials of the structure may be alumina (Al₂O₃), aluminum nitride (AlN), silicon nitride (Si₃N₄), or the like.

The housing 800 may be formed of an insulating material, synthetic material, or the like. In one aspect the housing 800 may be a plastic material. In one aspect, the housing 800 may be formed in an injection molding process with reinforced high temperature plastic. The housing 800 may serve a number of functions in addition to being a protective barrier to the power devices 500. These may include voltage blocking, mechanical support, guides for the power contacts, entry zones for gel passivation, vents for a gel passivation process, self-strengthening internal ribs, and the like.

The gate-source PCB 600 may include independent electrical paths for each switch position that may be required to form gate and source kelvin connections for controlling the power devices 500. In one aspect, the gate-source PCB 600 may be placed over the power substrate 300 and then connected to the base plate 200. The gate-source PCB 600 may include attachments for the gate drive connectors 700. The gate drive connectors 700 may be configured to connect to the signal line 106 in order to receive drive signals from the gate driver 102. The gate-source PCB 600 may provide the drive signals from the gate drive connectors 700 to the power devices 500.

FIG. 2A illustrates a schematic view of an implementation of the power module of FIG. 1. In particular, FIG. 2A shows an implementation of the clamp circuit 104 implemented as a Miller Clamp. The clamp circuit 104 may include a transistor 202 tied to the signal line 106 and to a source/emitter 206 of the power device 500. This implementation may enable a 0 V turn off drive that can simplify the gate driver 102 implementation. The FIG. 2A implementation shorts a gate of the power device 500 to the source/emitter 206 when implemented. Additionally, FIG. 2A illustrates that the clamp circuit 104 is arranged in close physical proximity to the power module 100. In particular, the clamp circuit 104 is arranged within the power module 100 as described above in relation to FIG. 1. This close physical proximity arrangement providing a number of benefits including the benefits described above. As further shown in FIG. 2A, the power module 100 may further include a sense and control circuit 214. The sense and control circuit 214 sensing current, voltage, and/or the like within the power module 100 and controlling the clamp circuit 104 in response thereto. In one aspect, the sense and control circuit 214 may sense a voltage and/or current on the signal line 106 and enable or disable the clamp circuit 104 accordingly. In one aspect, the sense and control circuit 214 may detect the gate driver 102 drive signal on the signal line 106 and disable the clamp circuit 104. Furthermore, the sense and control circuit 214 may detect the lack of the gate driver 102 drive signal on the signal line 106 and enable the clamp circuit 104. Of course other types of control logic are contemplated as well.

In the FIG. 2A aspect, the power device 500 may be a power FET that includes a transistor 220. Of course other types of power devices 500 are contemplated as well as described above. The power device 500 in the FIG. 2A implementation includes a drain/collector 204 and the source/emitter 206. The power device 500 may further include a capacitor 212 connected between the drain/collector 204 and the source/emitter 206. The power device 500 may further include a capacitor 208 connected between the drain/collector 204 and the signal line 106. The power device 500 may further include a capacitor 210 connected between the source/emitter 206 and the signal line 106. Of course other circuit arrangements are contemplated as well for the power devices 500.

FIG. 3 illustrates an exemplary sense and control circuit according to one aspect of the disclosure. In particular, FIG. 3 illustrates a sense and control circuit 214 implemented as a RC (resistor-capacitor) circuit. In this aspect, the sense and control circuit 214 may receive the gate driver 102 drive signal at an input 370 from the signal line 106 and output 372 a clamp circuit actuation signal to enable the clamp circuit 104. In one aspect, the FIG. 3 implementation of the sense and control circuit 214 may be implemented with a falling edge delay and rising edge pass through operation. In one aspect, the FIG. 3 implementation of the sense and control circuit 214 may be implemented with a diode 362 in parallel with a resistor 364. The output of the diode 362 and the resistor 364 may be tied to a capacitor 366 and a buffer 368. The buffer 368 may provide the drive signal to the clamp circuit 104 at the output 372.

In this regard, utilizing a RC time constant, a tunable delay can be introduced in a turn-off event of the sense and control circuit 214. This translates to a delay from when the power device 500 is signaled off to when the output 372 actuates the clamp circuit 104. In some aspects, when the power device 500 is commanded on, it may not desirable for the clamp circuit 104 to be engaged, so no rising edge delay may be introduced. In some aspects, the tunable RC time constant may be adjustable via a trimmer potentiometer implementation of the resistor 364. In this regard, the amount of a delay from when the power device 500 is signaled off to when the output 372 actuates the clamp circuit 104 may be adjusted by changing the resistance of the resistor 364 by adjustment of the trimmer potentiometer.

FIG. 2A further illustrates an exemplary structure of the gate driver 102. The gate driver 102 may include one or more transistors 218 tied to V+ and V−. The gate driver 102 may further include circuit elements 216. The circuit elements 216 may be implemented with a series resistor R_(G) and/or inductor L_(GS). Other components for the gate driver 102 are contemplated as well.

FIG. 2B illustrates a schematic view of another implementation of the power module of FIG. 1. In particular, FIG. 2B shows an implementation of the clamp circuit 104 implemented as a Miller Clamp. The clamp circuit 104 may include a transistor 302 tied to the signal line 106 and V−. This implementation holds the gate of the power device 500 off with a −V bias. This implementation has been found to provide improved hold-off capability. Additionally, FIG. 2B illustrates that the clamp circuit 104 is arranged in close physical proximity to the power module 100. In particular, the clamp circuit 104 is arranged within the power module 100 as described above in relation to FIG. 1. This close physical proximity arrangement providing a number of benefits including the benefits described above.

FIG. 4 illustrates a structural implementation of the power module of FIG. 1; FIG. 5 illustrates an exploded view of the power module of FIG. 4; and FIG. 6 illustrates a relative size to thickness comparison of the power module of FIG. 4.

The power module 100 may be configurable in multiple useful power electronic topologies such as half bridge, full bridge, common source/emitter, and common drain/collector and can be configured in two, four, and six separate channels. Moreover, the power module 100 can be configured with any number of separate channels.

The power module 100 may include a number of elements as described in relation to FIG. 1. These elements may include the base plate 200, the power substrate 300, the power contacts 400, the power devices 500, the gate-source PCB 600, the gate drive connectors 700, the housing 800, and the like. The power module 100 may further include one or more fasteners 900 for securing electrical connections. Additionally, as shown in FIG. 5, the clamp circuit 104 may be arranged on the gate-source PCB 600.

In one aspect, the power module 100 may be configured with a footprint common in the power electronics industry. In one aspect, the footprint of the power module 100 may be implemented with a 62 mm×107 mm base plate 200 with M6 mounting holes arranged 48 mm×93 mm apart. In one aspect, using a common footprint allows for customers with existing systems to utilize the power module 100 without investing in a system redesign. Of course, other size implementations are contemplated as well.

While in some aspects the length and width of the power module 100 fits industry standards, the height of the power module 100 may be two times to three times thinner than prior art implementations. In one aspect, the power module may be 15 mm or less in thickness. In one aspect, the power module may be 13 mm or less in thickness. In one aspect, the power module may be 10 mm or less in thickness. This dramatically reduces the power module inductance and increases current carrying capability partially by utilizing lower path lengths. It may also provide a major source of system level volume savings in a power converter or other application.

The comparison of top size to thickness dimensions of the power module 100 are presented in FIG. 6 in the top and side view comparison. In one aspect, the power module 100 measures 65 mm×110 mm×10 mm. The housing 800 may extend like a sheath over the base plate 200 for voltage isolation, which accounts for an extra 3 mm on each side over the base plate 200 dimensions. In one aspect, the power module 100 may have a volume of 71.5 cm³ and weigh approximately 140 g. In another aspect, the power module 100 measures 65 mm×110 mm×less than or equal to 13 mm. In another aspect, the power module 100 measures 65 mm×110 mm×less than or equal to 15 mm.

In one aspect, the power module 100 may utilize 57.5 mm×73 mm, 42 cm², of the total footprint area for conduction. This is a 60% utilization solely for current carrying. The remaining area may be used for mounting, 5%, gate drive connections, 5%, and plastic features including minimum wall thickness, voltage creepage extenders, and strengthening ribs, 30%.

FIG. 7 illustrates a current flow for multiple paralleled devices of the power module of FIG. 4. As shown in FIG. 7, a power loop 710 of the power module 100 may be configured for effectively paralleling large numbers of power devices 500. In particular, FIG. 7 shows power devices 501-511. Nevertheless, it is contemplated that the power module 100 may include any number of power devices 500. In some aspects, the power module 100 can either have two, four, or more switch positions, depending on its configuration, which is detailed later. Moreover, the power module 100 can be configured with any number of switch positions. FIG. 7 shows an upper position 480 and a lower position 490. There is a large amount of flexibility in the formation of each switch position, such that they may be tailored to specific applications without costly power module 100 modifications. For example, the positions may have an equal number of diodes to the power devices 500, only a few diodes, or none at all. FIG. 7 is a representation of the power loop 710, depicting the even, shared current paths 120 for current traveling from the “V+” terminal 410 (400) to the “Mid” terminal 420 (400), the “V−” terminal 430 (400) is also shown that is used for power devices 500 in the lower position 490. An additional benefit of this layout is that the even spacing of each power device 500 aids in the spreading of the heat sources across the power module 100 instead of concentrating them in a few locations.

As further shown in FIG. 7, in certain aspects nearly the entire width of the power module 100 is utilized for the conduction of current. Many benefits would be lost if the power module 100 was tall. In the worst case, the length the current would travel through the power contact 410, 420, 430 would be longer than the path it travels once it reaches the power substrates 300. Accordingly, the power contacts 400 may be configured and designed to have a low height such that they contribute a negligible amount to the resistance and inductance of the system.

FIG. 8 illustrates the power contact configuration of the power module of FIG. 4. In one aspect, the power contacts 400 may have a low height. The low height of the power contacts 400 may be achieved by using a dual bending process. First, the power contacts 400 may be formed through a metal stamping operation, by etching, or the like followed by forming in a press brake. A 90° bend at the base 450 creates an “L” shaped connector with a vertical body 460. The base 450 may be soldered down to the power substrates 300. The base 450 may be configured to be relatively thin in comparison to the overall shape. This reduces the area consumed by this bond, allowing for more active power device 500 area inside of the power module 100. To improve adhesion of this thin bond, staggered holes or solder catches 454 may be etched or formed along the bonding surface 452 on the bottom of the base 450. During manufacturing, molten solder may travel up the solder catches 454 through capillary action. Once solidified, the solder inside of the solder catches 454 substantially improves bond strength in many directions. An exemplary power contact 400 with solder catches 454 is illustrated in FIG. 8.

Also shown in FIG. 8 is illustrated the manner in which the “L” shaped power contacts 400 may be bent a second time at the end of the fabrication process to form a contact top 470. Before bending, the vertical body 460 of the power contact 400 may allow for the housing 800 to be dropped into place, as there are no undercuts present. In certain aspects, the housing 800 may be a single piece plastic housing. The radius of the second bend 472 may not be as large as the first bend 462. This provides some tolerance in the process and may result in a smoother bending operation. The second radius 472 may be facilitated through a pre-formed radius 810 in the plastic housing 800, which, at this stage, may be touching the leading edge 464 of the power contacts 400. Specifically designed rotating bending hardware may press flatly on the opposite surface 466, folding the power contacts 400 down over the captive fasteners 900. An illustration of the bending of the “L” shaped contacts into “C” shaped forms is illustrated in FIG. 9 by the curved arrow.

Underneath the folded power contacts 400 may be arranged low profile fasteners 900 and in one aspect, the fasteners 900 may be threaded. For example, the fasteners may be nuts. These fasteners 900 may be captured underneath the power contacts 400. The fasteners 900 may otherwise be loose. The captive fasteners 900 may be arranged such that when the power module 100 is bolted to buss bars, the fasteners 900 and the power contacts 400 are pulled upwards into the bussing, forming a better quality electrical connection. If the fasteners 900 were affixed to the housing 800, they could act to pull the bussing down into the power module 100, which could form a poor connection due to the stiffness of the buss bars.

FIG. 10 illustrates the power module base plate of the power module of FIG. 4. In particular, FIG. 10 shows how the power module 100 base plate 200 may be configured to match an industry standard 62 mm geometry, which has a set diameter and location for the mounting holes 203 in the corners. The thickness of the base plate 200 in some aspects may be fine-tuned through the use of parametric finite element analysis of a CAD model. This may be achieved by sweeping the thickness between pre-defined practical limits and measuring the thermal and mechanical responses. The material and thickness combinations that achieves the best thermal performance with a minimal mechanical deflection may then be selected. Additional features of the power module 100 plate may be machined or molded, depending on the MMC material, to include standoffs 240, which may include a threaded board hole 242 and a housing hole 290. The standoff 240 may provide a planar surface with the power substrate 300 such that the gate-source PCB 600 can be bolted down without bowing.

FIG. 11 illustrates the gate-source PCB secondary substrate of the power module of FIG. 4. The gate-source PCB 600 may include independent electrical paths for each switch position that may be required to form gate and source kelvin connections, which may be necessary for controlling the power devices 500. Additionally, the gate-source PCB 600 may include the clamp circuit 104. The power devices 500 may be arranged in parallel with the gate and source kelvin routing configured such as to not interfere with the wide, equalized power paths. FIG. 11 shows how the power module 100 and its variations may include a single piece secondary gate-source PCB 600 which may be placed over the power substrate 300 and then may be fastened to the base plate 200.

As shown in FIGS. 11 through 15, the gate-source PCB 600 may have two interconnection channels 602, 604 that may be located in one of four positions: top or first 611, upper middle or second 612, lower middle or third 613, and bottom or fourth 614 to define die apertures such as an external die aperture 603 or middle die aperture 605 to allow for a multitude of power module 100 configurations. The gate-source PCB 600 may utilize other positions and interconnection channels as needed. Essentially, the relative layout of each interconnection channel 602, 604 may be the same. However, the location and direction may be adapted to match the associated die aperture 603, 605 and the power device 500 placement and rotation to match each topology. This is illustrated in FIG. 12, FIG. 13, and FIG. 14 with the arrows indicating the gate direction for a half bridge, common source/emitter, and common drain/collector topology, respectively. Each of these may include a single or dual channel arrangement, depending on the layout of the power substrate 300 and the format of the power contacts 400 and housing 800.

As shown in FIG. 15, to aid in paralleling, individual ballast resistors 640 may be included on the gate-source PCB 600. While there are many different layouts these boards can utilize such as parallel planes, clock tree distribution, etc., one of the more effective is a low cost single layer modular arrangement with many bonding locations 642. As shown, a gate track 650 and source track 652 may extend across the length of the interconnection channels 654. Source wire bonds may be formed directly on the source track 652. Each gate may be bonded to individual gate pads 651, which may be connected to the gate track through resistors 640. The values of the resistors 640 are device and application dependent and will vary between power module 100 configurations.

FIG. 16 illustrates the power substrate half bridge arrangement of the power module of FIG. 4; FIG. 17 illustrates the power substrate common source/emitter arrangement of the power module of FIG. 4; and FIG. 18 illustrates the power substrate common drain/collector arrangement of the power module of FIG. 4. In particular, FIG. 16 shows the power substrate 300. The metal layers 304 may be etched into topology specific patterns 330, 340, 350 as illustrated in FIG. 16 for a half bridge substrate 330, FIG. 17 for a common source/emitter substrate 340, and FIG. 18 for a common drain/collector substrate 350 showing the upper and lower device 500 positions for each configuration. Also note that each of these layouts may be split into a dual channel arrangement by etching a line down the center of the power substrates 300. They may also be split into individual substrates per channel if desired. This may be useful for more harsh environments as the smaller substrates will experience less stress.

FIG. 19 illustrates the housing topside features of the power module of FIG. 4; and FIG. 20 illustrates the housing backside features of the power module of FIG. 4.

The housing 800 may be formed in an injection molding process with reinforced high temperature plastic. The housing 800 may serve many functions in addition to being a protective barrier to the sensitive power devices 500. This includes voltage blocking, mechanical support for the captive fasteners 900, guides for the power contact bending process, entry zones for gel passivation, vents for the gel passivation process, and self-strengthening internal ribs 812. Many of these features are depicted in FIG. 19 and FIG. 20. High aspect ratio trenches may be placed around the periphery of the power contacts 400 to increase the surface distance between exposed metal contacts, increasing voltage blocking capability.

FIG. 19 shows the high temperature plastic housing topside features including the creepage extenders 802, the passivation entries and vents 804, the captive fasteners apertures 806, the labeling area 808, and the power contact pinch and radius 810. FIG. 20 shows the backside features including the strengthening ribs 812, the thick bolt hole core sections 814, the bolt head clearance recess 816, the bottoms of the fastener insets 818, the power contact entryways 820, and the wire bond clearance apertures 822.

FIG. 21 illustrates the housing separated from the power module assembly of the power module of FIG. 4; and FIG. 22 illustrates the power contact guides of the power module of FIG. 4.

FIG. 21 shows how the housing 800 slides over the electronic sub assembly to form the top of the power module 100, with the power contacts 400 routed through the narrow openings or slots 820. The housing 800 may be bolted 830 at two points to threaded housing holes 290 on the base plate 200. At this stage the gel passivation material may be injected into the power module 100 and fully cured. Multiple openings and vents 804 assist this assembly step. The slots 820 in the housing 800 for the power contacts 400 have drafted “guides” to aid this process, and a rounded fillet 810 on top to aid in the bending procedure. These are illustrated in FIG. 22.

As discussed earlier, the power module 100 is configurable in a variety of useful power electronic topologies. These include half bridge, common source/emitter, and common drain/collector. Splitting the channels, through layout changes in the power substrate 300 and gate-source PCB 600 and alterations to the power contacts 400 and housing 800, allows three more configurations, including a full bridge, common source/emitter dual channel, and common drain/collector dual channel.

FIG. 23 illustrates the half bridge, single channel common source or drain/collector module of the power module of FIG. 4; FIG. 24 illustrates the full bridge, dual channel common source/emitter or drain/collector module of the power module according to another aspect of the disclosure; and FIG. 25 illustrates the extended single housing side-by-side module configuration of the power module according to another aspect of the disclosure.

FIG. 23 illustrates the first external configuration 150 for half bridge, single channel common source/emitter, and single channel common drain/collector configurations. There are four locations 701, 702, 703, 704 for the gate drive connections 700, two on each side. Either or both sides may be used for this purpose. For the dual channel arrangement 152, shown in FIG. 24, the power contacts 400 are split and provide two fully isolated channels. Gate drive connectors 700 on both sides may now be required. This arrangement is used for a full bridge, dual channel common source/emitter, and dual channel common drain/collector topologies.

For higher currents and for customers who desire a single module, a larger side-by-side arrangement of a dual power module 2500 may be fabricated from two modules built side by side into a single housing 800. This is illustrated in FIG. 25.

Experimental Results

FIG. 26 illustrates a clamped inductive load (CIL) test fixture schematic to provide test performance data for power modules. In order to verify the performance of the clamping circuit 104, a CIL test fixture 1 was utilized. Since the performance criteria for the clamping circuit 104 testing are gate voltages of a power module 6, differential probes were not utilized due susceptibility to common mode noise. To be able to measure the gate performance of the power module 6 accurately, without the differential probes, only the voltage of a low side device 4 was measured.

The schematic representation of the CIL test fixture 1 is illustrated in FIG. 26 where an inductive load 2 is tied from a midpoint 5 of a half bridge of the power module 6 to a source of the low side device 4 of the power module 6. An upper device 3 will turn-on, causing the midpoint voltage to sharply rise to a bus voltage. FIG. 26 further illustrates a pair of capacitors 7 (C_(BULK) AND C_(HF)) in parallel with a resistor 8 (CVR).

This arrangement and operation of the CIL test fixture 1 theoretically created a maximum voltage disturbance on the low side device 4. Since a portion of an associated gate-source kelvin PCB is dedicated to signal connections that connect the power module 6 to the gate driver, some of the side pads were utilized to create kelvin test points for the gate-source voltage measurement. This measurement approach enabled a clean, representative voltage waveform and theoretically did not include any affects of inductance introduced by the gate driver to power module 6 interconnection.

First, a control sample was tested. A commercial gate driver was tested with a custom CAS325M12HM2 power module 6 (1200V, 325 A, Silicon Carbide High-Performance 62 mm Half-Bridge Module manufactured by Wolfspeed, Fayetteville, Ark.) without anti-parallel Schottky diodes. On the gate driver, a 0Ω turn-on resistor was used along with a 5Ω turn-off resistor. This gate resistor arrangement was chosen to reduce turn-on loss and to limit turn-off voltage overshoot. A bus voltage was chosen to be 800 V with a drain current of 400 A. The gate voltage of the low side device 4 is shown in the lower graph of FIGS. 27-29 when the high side device is turned on.

FIG. 27 illustrates graphs of test data for a power module with no gate clamping. In particular, FIG. 27 illustrates a low side MOSFET drain voltage and current under forced commutation with no gate clamping (upper graph); and a MOSFET gate voltage under forced commutation with no gate clamping (lower graph). More specifically, FIG. 27 illustrates a low side MOSFET drain voltage and current (upper graph) with a vertical axis showing drain voltage in volts (V) and drain current in amps (A), and time in seconds (s) along the horizontal axis; and FIG. 27 further illustrates the MOSFET gate voltage (lower graph) with the vertical axis showing gate voltage in volts (V) and time in seconds (s) along the horizontal axis. As shown in FIG. 27, the gate voltage spikes to +5 V which is above the threshold voltage of the device. The unused gate-source pins of the power module 6 were used as a kelvin contact to eliminate as much coupling as possible. From the measurements on the gate, it is clear that the devices inside the power module 6 do experience a Miller induced charge-up, but not to the point of shoot through. FIG. 27 further illustrates that the peak voltage rise is from −6 V to +5 V which is a rise of 11 V. This is 11 volts from the desired −6 V. Moreover, FIG. 27 illustrates that the peak to peak voltage is 11 V.

FIG. 28 illustrates graphs of test data for a power module with a clamping circuit located on a gate driver. In particular, FIG. 28 illustrates a low side MOSFET drain voltage and current under forced commutation with a clamping circuit located on the gate driver (upper graph); and a MOSFET gate voltage under forced commutation with a clamping circuit again located on the gate driver (lower graph). More specifically, FIG. 28 illustrates a low side MOSFET drain voltage (upper graph) with the vertical axis showing drain voltage in volts (V) and drain current in amps (A), and time in seconds (s) along the horizontal axis; and a MOSFET gate voltage (lower graph) with the vertical axis showing gate voltage in volts (V) and time in seconds (s) along the horizontal axis.

In the FIG. 28 implementation, the modified gate driver was tested with the clamp circuit located on the gate driver board (but not inside the module). The driver and power module 6 were tested under the same conditions. The results in FIG. 28 show that the introduction of the clamp circuit on the gate driver PCB slightly reduces the overshoot seen at the gate of the devices by approximately 0.4 V. The gate now peaks at approximately 4.6 V, which is still above the threshold voltage of the devices. Since the clamp circuit is located between the gate resistors and the MOSFETs, it is apparent that sizing the turn-off MOSFET with a lower value will not help reduce Miller induced charge-up. The clamp circuit is able to provide a very low-impedance path to the negative rail, but the interconnect impedance between the gate driver and the power devices is now dominating. This indicates that if a clamp circuit must be located on the gate driver, the only way to eliminate the voltage spike seen on the gate of the power module 6 is to reduce the interconnect inductance, which is commonly not feasible due to bus bar creepage, clearance constraints, and the like. FIG. 28 further illustrates that the peak voltage rise is from −6 V to +4.6 V which is a rise of 10.6 V. This is 10.6 V from the desired −6 V. Moreover, FIG. 27 illustrates that the peak to peak voltage is approximately 13.6 V.

FIG. 29 illustrates graphs of test data for a power module with a clamping circuit located with the power module in accordance with the disclosure. In particular, FIG. 29 illustrates a low side MOSFET drain voltage and current under forced commutation with clamping circuit located inside the power module (upper graph) in accordance with the disclosure; and a MOSFET gate voltage under forced commutation with clamping circuit again located inside the module (lower graph) in accordance with the disclosure. More specifically, FIG. 29 illustrates a low side MOSFET drain voltage (upper graph) with the vertical axis showing drain voltage in volts (V) and drain current in amps (A), and time in seconds (s) along the horizontal axis; and a MOSFET gate voltage (lower graph) with the vertical axis showing gate voltage in volts (V) and time in seconds (s) along the horizontal axis.

The power module 6 with the integrated clamping circuit implementation in accordance with the disclosure was tested under the same voltage and current conditions.

As illustrated in FIG. 29, a maximum gate voltage was −2 volts. FIG. 29 further illustrates that the peak voltage rise is from −6 V to −2 V which is a rise of 4 V. This is 4 V from the desired −6 V. Moreover, FIG. 29 illustrates that the peak to peak voltage is approximately 8 V. A rise of 4 V is 64% less than the implementation having no clamping circuit associated with FIG. 27 and 62% less than the implementation with a clamping circuit on the gate driver associated with FIG. 28. Moreover, the peak to peak voltage as shown in FIG. 29 is 8 V, which is 27% less than the implementation associated with FIG. 28 and 41% less than the implementation associated with FIG. 27.

The implementation of the clamping circuit according to the disclosure had nearly direct access to the MOSFET's gates and thus is able to dramatically reduce the voltage charge-up seen on the gate. The gate voltage rises to approximately −2 V which is more than adequate negative bias. The clamp circuit is able to ensure the gates remain under control even under worst case conditions. The drain voltage dv/dt was pushed to extremely high speed to replicate extreme conditions in order to prove the performance of the clamping circuit under the most demanding conditions.

Based on the experimental results shown, there is a compelling reason to include a clamping circuit in high-performance power modules. Excellent gate control is possible without introducing much additional complexity to the gate driver of the power module. Since the clamping circuit is a realized by a small signal device, such as a MOSFET, there is little incurred extra cost by adding such a device. Moreover, it should be appreciated that the beneficial performance of the clamping circuit arrangement in the power module would likewise extend to implementations utilizing different voltages and different currents. In this regard, the disclosure should not be limited to the particular voltages and currents tested. The disclosure contemplates benefits to other possible voltages and currents.

In an additional aspect of the disclosure, the clamping circuit 104 may be integrated with the power module 100 to simplify gate driver requirements even further. In this regard, the clamping circuit 104 may be further integrated with control logic of the sense and control circuit 214 inside the power module 100 so that no additional gate drive circuitry may be required from the customer side. This may require a more significant gate-source kelvin PCB with additional components, but the simplification from a user standpoint is worth the additional one-time design complexity. In further aspects, aspects of the disclosure may allow for simplification of the gate driver circuitry, which may include the ability to eliminate a negative gate rail. Since the clamping circuit 104 demonstrates very good gate control capability, it is possible to drive the power devices, such as a MOSFET, to a 0 V level and utilize the integrated clamping circuit 104 to ensure the device is held off. Elimination of the negative rail may reduce the power supply requirement on the gate driver itself, which reduces cost and complexity. Simplification of the gate driver power supply requirements has the potential to enable power devices, such as SiC MOSFETs, to run on standard Si gate drive rails and ICs. Accordingly, the disclosure has set forth an improved power module 100 having an integrated clamp circuit having numerous benefits described herein. For example, the placing of the clamp circuit 104 in close physical proximity to the power module 100 improves performance of the power devices 500. Moreover, placing the clamp circuit 104 in close physical proximity to the power module 100 reduces customer complexity with respect to operation and control of the power module 100. Applications of the power module 100 include motor drives, solar inverters, circuit breakers, protection circuits, DC-DC converters, and the like.

Aspects of the disclosure have been described above with reference to the accompanying drawings, in which aspects of the disclosure are shown. It will be appreciated, however, that this disclosure may, however, be embodied in many different forms and should not be construed as limited to the aspects set forth above. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the disclosure. The term “and/or” includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “top” or “bottom” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Aspects of the disclosure are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected.

In the drawings and specification, there have been disclosed typical aspects of the disclosure and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the disclosure being set forth in the following claims.

While the disclosure has been described in terms of exemplary aspects, those skilled in the art will recognize that the disclosure can be practiced with modifications in the spirit and scope of the appended claims. These examples given above are merely illustrative and are not meant to be an exhaustive list of all possible designs, aspects, applications or modifications of the disclosure. In this regard, the various aspects, features, components, elements, modules, arrangements, circuits, and the like are contemplated to be interchangeable, mixed, matched, combined, and the like. In this regard, the different features of the disclosure are modular and can be mixed and matched with each other. 

1. A power module apparatus, comprising: a power substrate; at least one power device electrically connected to the power substrate; a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device; a housing secured to the power substrate; a clamping circuit electrically connected to the at least one power device; and the clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.
 2. The power module apparatus of claim 1, wherein the clamping circuit comprises a Miller clamp.
 3. The power module apparatus of claim 1, wherein the clamping circuit is configured to clamp an input to the gate of the at least one power device; and wherein the clamping circuit is integrated in the power module apparatus and the clamping circuit is arranged with at least one of the following: a base plate, the power substrate, one of at least two power contacts, the at least one power device, the gate-source board, gate drive connectors, and the housing.
 4. The power module apparatus of claim 2, wherein the clamping circuit is configured to clamp a voltage at the gate of the at least one power device to less than 8 V peak to peak.
 5. The power module apparatus of claim 4, wherein the clamping circuit comprises a transistor discretely holding the at least one power device off; wherein the transistor is connected to the gate of the at least one power device; and wherein the transistor is connected to at least one of the following: a source/emitter of the at least one power device and a negative voltage bias (−V).
 6. The power module apparatus of claim 1, further comprising a sense and control circuit electrically connected to the clamping circuit, the sense and control circuit configured to control the clamping circuit as a function of a driver control signal.
 7. The power module apparatus of claim 6, wherein the sense and control circuit is configured to control the clamping circuit as a function of the driver control signal based on a falling edge delay and rising edge pass through operation.
 8. The power module apparatus of claim 1 wherein the clamping circuit is configured to reduce the voltage charge up at the gate of the at least one power device by at least 10%.
 9. The power module apparatus of claim 1, wherein the clamping circuit is configured to reduce a voltage charge up at a gate of the at least one power device to within 6 V of a desired voltage.
 10. A power module apparatus, comprising: a power substrate positioned relative to a base plate; at least one power device electrically connected to at least two power contacts; a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device; a clamping circuit electrically connected to the at least one power device, the clamping circuit configured to clamp an input to a gate of the at least one power device, wherein the clamping circuit is configured to clamp a voltage at the gate of the at least one power device to less than 10 V peak to peak.
 11. The power module apparatus of claim 10, wherein the clamping circuit comprises a Miller clamp.
 12. The power module apparatus of claim 10, wherein the clamping circuit is integrated in the power module apparatus and the clamping circuit is arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, gate drive connectors, and a housing.
 13. The power module apparatus of claim 11, wherein the clamping circuit comprises a transistor discretely holding the at least one power device off; wherein the transistor is connected to the gate of the at least one power device; and wherein the transistor is connected to at least one of the following: a source/emitter of the at least one power device and a negative voltage bias (−V).
 14. The power module apparatus of claim 13, wherein the clamping circuit is configured to clamp a voltage at the gate of the at least one power device to less than 8 V peak to peak.
 15. The power module apparatus of claim 10, further comprising a sense and control circuit electrically connected to the clamping circuit, the sense and control circuit configured to control the clamping circuit as a function of a driver control signal.
 16. A power module apparatus, comprising: a power substrate positioned relative to a base plate; at least one power device electrically connected to at least two power contacts; a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device; and a clamping circuit electrically connected to the at least one power device, the clamping circuit configured to clamp an input to a gate of the at least one power device, wherein the clamping circuit is configured to reduce a voltage charge up at the gate of the at least one power device by at least 10%.
 17. The power module apparatus of claim 16, wherein the clamping circuit comprises a Miller clamp.
 18. The power module apparatus of claim 16, wherein the clamping circuit is integrated in the power module apparatus and the clamping circuit is arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, gate drive connectors, and a housing.
 19. The power module apparatus of claim 17, wherein the clamping circuit comprises a transistor discretely holding the at least one power device off; wherein the transistor is connected to the gate of the at least one power device; and wherein the transistor is connected to at least one of the following: a source/emitter of the at least one power device and a negative voltage bias (−V).
 20. The power module apparatus of claim 16, wherein the clamping circuit is configured to reduce the voltage charge up at the gate of the at least one power device by at least 30%. 